1. Field of the Invention
The present invention relates in general to a wobble clock generator and a related driving method, and more particularly, to a wobble clock generator and a related driving method having a shared oscillating signal utilized to generate a wobble clock and to act as a reference clock for a protective mechanism capable of avoiding interference generated from a phase-modulated wobble signal.
2. Description of the Prior Art
Over the past few years, storage media have rapidly increased in storage capacity due to demand for storing a tremendous amount of information. Of all the various kinds of storage media, optical discs have features of a low-cost, small-size, low-error-rate, long-storage-time, and high-density storage medium and is the most promising dominant storage medium in the future. Generally speaking, optical disc drives are used to read information stored on an optical disc. Examples of optical disc drives are known as compact disc drives (CD-ROM drives) and digital versatile disc drives (DVD-ROM drives) in the prior art. Some optical disc drives have the additional capability of being able to write data onto an optical disc, i.e., CD-R/RW, DVD+R/RW and DVD-R/RW drivers. Optical disc drives are used in music and video playback and are implemented in recording devices and other electronic devices.
In order to effectively manage the information stored on a digital versatile disc, the data storage region of the digital versatile disc is divided into many frames. Data can be stored in these frames according to a memory format. Therefore, while in a writing process for a rewritable digital versatile disc, the DVD drive has to identify the memory format of the rewritable digital versatile disc before the writing process. In order to record the related information concerning the memory frames, there are special addressing structures on the rewritable digital versatile disc to record the related information. According to the specifications of a recordable or a rewritable digital versatile disc, the related information recorded in the addressing structures is known as the address in pre-groove (ADIP).
Please refer to FIG. 1. FIG. 1 is a schematic diagram showing a reading process on a reflecting surface of an optical disc by an optical pickup 31. On the reflecting surface of the optical disc, there is a fine spiral track 11 as is shown in FIG. 1. The fine track 11 is composed of two types of tracks, one being a data track 26 to record data, and the other being a wobble track 28 to record related addressing information of each frame.
As illustrated in the magnified view of FIG. 1, the data track 26 has an interrupt and discontinuity record mark 30, and the wobble track 28 has an oscillating shape. The surface of the wobble track 28 protrudes beyond the reflecting surface of the optical disc. The data track 26 is located inside a groove formed by the raised wobble track 28 as is shown in FIG. 1. The length of each record mark 30 varies, and the reflection characteristic of the record mark 30 is different from that of the other reflecting surface of the optical disc.
The optical pickup 31 comprises an optical receiver (not shown) for reading the data from the record mark 30 within the data track 26, and four optical sensors Sa, Sb, Sc, and Sd to extract tracking information from the wobble track 28. The positions of the sensors Sa and Sd in FIG. 1 are located on the groove area of the fine track 11 on the reflecting surface of the optical disc. However, the positions of the sensors Sb and Sc in FIG. 1 are located on the protruded area of the fine track 11.
As the optical disc rotates, the optical pickup 31 can be thought of as moving over the fine track 11 of the optical disc along the direction of arrow 32. The reflected laser beam intensities detected by the four sensors Sa, Sb, Sc, and Sd are different because of the difference in reflecting quality between the groove and the protruded area of the wobble track 28. As the optical pickup 31 moves along a straight path from the position shown to a position P1, the sensing values of the four sensors Sa, Sb, Sc, and Sd change. In other words, while the optical pickup 31 is located at the position P1, the positions of the sensors Sa and Sd are changed to be located on the protruded area of the fine track 11 and the positions of the sensors Sb and Sb are changed to be located on the groove area of the fine track 11.
By performing some well-known subtracting processes over the electrical sensing values of the four sensors Sa, Sb, Sc, and Sd, a wobble signal can be generated. Thereafter, the wobble signal can be utilized to generate an address in pre-groove (ADIP) through a decoding process.
It is well-known that the information of the ADIP is recorded in the wobble signal by a phase modulation technique, which means that the information is recorded according to the phase shift of a carrier. Every pair of record areas on an optical disc corresponds to 93 wobble cycles, and 8 wobble cycles of them are utilized to record an ADIP by phase modulation.
As aforementioned, since the ADIP is recorded in the wobble signal by phase modulation, an ADIP decoder is required for the disc drive to extract the ADIP from an optical disc. Please refer to FIG. 2. FIG. 2 shows a functional block diagram of a prior art analog ADIP decoder 40. The ADIP decoder 40 comprises a delay circuit 42, a mixer 44, a phase-locked loop (PLL) 46, a frequency divider 48, and an XOR operation logic circuit 50.
First of all, the functional operation of the analog ADIP decoder is processed based on the following trigonometric expression.
                                          Sin            ⁡                          (              θ              )                                *                      Cos            ⁡                          (              θ              )                                      =                              1            2                    ⁢                      Sin            ⁡                          (                              2                ⁢                θ                            )                                                          eq        .                                  ⁢                  (          1          )                    Wherein Sin(θ) is used to describe the waveform of a wobble signal and Cos(θ) is used to described the waveform of the other signal.
Therefore, if a phase shift of 180° of the wobble signal occurs, which means the corresponding waveform of the wobble signal becomes Sin(θ+180°), another signal with a waveform of 0.5*Sin(2θ+360°) is generated according to eq. (1). The waveform function 0.5*Sin(2θ+360°) is actually equal to 0.5*Sin(2θ). In other words, a non-phase-modulated wobble clock can be generated by a phase-modulated wobble signal. After the wobble clock is generated, the ADIP decoder is able to extract the ADIP based on the wobble signal in conjunction with the wobble clock.
As is shown in FIG. 2, the signal S1 is a wobble signal. A signal S2 is generated by performing a quarter cycle delay process on the signal S1 by the delayed circuit 42, which causes a phase difference of 90° between the signal S1 and the signal S2. If the waveform of the signal S1 corresponds to Sin(θ), the corresponding waveform of the signal S2 becomes Sin(θ+90°) which is actually equal to Cos(θ). Thereafter, the signal S1 is multiplied by the signal S2 through the mixer 44 to generate a signal S3. As aforementioned, the waveform of the signal S3 then corresponds to the function 0.5*Sin(2θ), which means the frequency of the signal S3 is twice as high as the frequency of the signal S1. With the help of the signal S3, the phase-locked loop 46 is able to generate a signal S4 which is synchronized with the signal S3. The waveform of the signal S4 also corresponds to the function Sin(2θ). Next, the frequency divider 48 generates a signal S5 with half the frequency of the signal S4.
Since the signal S5 is a non-phase-modulated wobble clock and the signal S1 is a phase-modulated wobble signal, after an XOR operation is performed on the signal S1 and the signal S5 by the XOR operation logic circuit 50, an ADIP is extracted from the signal S1.
Because there is no analog differentiator to convert Sin(θ) precisely into Cos(θ), the delay circuit 42 is utilized to perform the conversion. However, if the rotating speed of the optical disc keeps changing, the frequency of the signal S1 also changes accordingly. Therefore, the delay circuit 42 is required to adjust the delay parameters according to the changing cycles of the signal S1. Based on the functional demands described above, the delay circuit 42 becomes complicated and is hard to implement.
Please refer to FIG. 3. FIG. 3 shows a functional block diagram of a prior art digital ADIP decoder 60. The ADIP decoder 60 comprises an analog-to-digital converter (ADC) 62, a differentiator 64, a multiplier 66, a PLL 68, a frequency divider 70, and an XOR operation logic circuit 72. In a similar way described before, based on the eq. (1), the digital ADIP decoder 60 is able to generate a wobble clock from a wobble signal and extract an ADIP from the wobble signal.
Because the signal S1 is an analog wobble signal, the analog-to-digital converter 62 is required to convert the analog signal S1 into a digital signal S2 for further digital signal processing. The differentiator 64 generates a signal S3 by performing a differentiating process on the signal S2. In other words, if the analog signal S1 corresponds to a function Sin(θ), then the digital signal S2 should be a digital signal corresponding to the same function Sin(θ) and the digital signal S3 should be a digital signal corresponding to the function Cos(θ). Thereafter, the digital signal S2 is multiplied by the digital signal S3 through the multiplier 66 to generate a digital signal S4.
According to the eq. (1), the digital signal S4 corresponds to the function 0.5*Sin(2θ), which means the frequency of the digital signal S4 is twice as high as the frequency of the digital signal S2. With the aid of the digital signal S4, the phase-locked loop 68 is able to generate a digital signal S5, which is synchronized with the digital signal S4. Consequently, the digital signal S5 also corresponds to the function Sin(2θ). Thereafter, the frequency divider 70 generates a digital signal S6 with half the frequency of the digital signal S5.
Since the digital signal S6 corresponds to a non-phase-modulated wobble clock waveform and the digital signal S2 corresponds to a phase-modulated wobble signal, after an XOR operation is performed on the digital signal S2 and the digital signal S6 by the XOR operation logic circuit 72, an ADIP is extracted from the signal S2.
As aforementioned, the operation of the digital ADIP decoder 60 requires an analog-to-digital conversion and a digital differentiating process, which means the demand for ultra high speed operation of the circuits must be achieved to be integrated into a high-performance DVD drive. Furthermore, in order to achieve high resolution in the analog-to-digital converting process, higher bits per sampling signal data is another stringent requirement of the digital ADIP decoder 60 for a high-performance DVD drive. Again, because of the stringent requirements described above, the digital ADIP decoder 60 is actually a complicated and high-cost circuit for a high-performance DVD drive.